For more than three decades, the continued miniaturization of silicon metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. A concise summary of near-term and long-term challenges to continued CMOS scaling can be found in the “Grand Challenges” section of the 2002 Update of the International Technology Roadmap for Semiconductors (ITRS). A very thorough review of the device, material, circuit, and systems can be found in Proc. IEEE, Vol. 89, No. 3, March 2001, a special issue dedicated to the limits of semiconductor technology.
Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, methods for improving performance without scaling have become critical. One approach for doing this is to increase carrier (electron and/or hole) mobilities. Increased carrier mobility can be obtained, for example, by introducing an appropriate strain into the Si lattice.
The application of stress changes the lattice dimensions of the silicon (Si)-containing substrate. By changing the lattice dimensions, the energy gap of the material is changed as well. The change may only be slight in intrinsic semiconductors resulting in a small change in resistance, but when the semiconducting material is doped, i.e., n-type, and partially ionized, a very small change in energy bands can cause a large percentage change in the energy difference between the impurity levels and the band edge. Thus, the change in resistance of the semiconducting material with stress is large.
Compressive longitudinal stress along the channel increases drive current in p-type field effect transistors (pFET) and decreases drive current in n-type field effect transistors (nFET). Tensile longitudinal stress along the channel increases drive current in nFETs and decreases drive current in pFETs.
Nitride liners positioned atop field effect transistors (FETs) have been proposed as a means to provide stress based device improvements. Referring to FIG. 1, a prior field effect transistor (FET) 19 is provided including a nitride liner 15′ positioned on a gate region 5 and atop a planar substrate surface 33, in which the nitride liner 15′ produces a stress on the device channel 12. The device channel 12 is located between source/drain regions 6 and source/drain extension regions 7. The source/drain regions 6 further comprise silicide regions 11. The gate region 5 includes a polysilicon gate 3 atop a gate dielectric 2. Sidewall spacers 14 abut the gate region 5. The stress transfer in this prior FET is limited and the typical channel stress produced by the nitride liner 15′ ranges from about 150 MPa to about 200 MPa.
There is a continued need to produce higher stresses on the channel of the device than previously possible using nitride liners, in which the stress provides stress based device improvements.